Semiconductor memory apparatus and data input/output method thereof

ABSTRACT

A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority to Korean application number10-2009-0096881, filed on Oct. 12, 2009, which is incorporated byreference in its entirety as set forth in full.

BACKGROUND OF THE INVENTION

1. Technical Field

Embodiments of the present invention relate generally to a semiconductortechnology, and more particularly, to a semiconductor memory apparatusand a data input/output method thereof.

2. Related Art

To obtain high-speed operation of semiconductor memory, a plurality ofstacked memory banks constituting a stacked bank structure is beingemployed in the semiconductor memory apparatus to improve data accesstime. In a semiconductor memory apparatus having the stacked bankstructure, memory cell regions are partitioned into a plurality ofmemory blocks, and each of the partitioned memory blocks comprises aplurality of stacked memory banks.

FIG. 1 is a block diagram schematically showing a configuration of asemiconductor memory apparatus including stacked memory banks. As shownin FIG. 1, the semiconductor memory apparatus includes first and secondmemory banks Bank1 and Bank2, first and second column decoders 11 and12, and first and second input/output (I/O) drivers 21 and 22.Hereinafter, it is assumed that the first and second memory banks Bank1and Bank2 constitute the stacked bank structure.

The first column decoder 11 and the first input/output driver perform adata read or write (hereinafter, referred to as ‘read/write’) operationon the first memory bank Bank1, and the second column decoder 12 and thesecond input/output driver 22 perform a data read/write operation on thesecond memory bank Bank2. More specifically, in the data read/writeoperation on the first memory bank Bank1, the first column decoder 11generates, in response to column address signal ‘Ya<2:7, 9> and a strobesignal ‘strobe<0>, a column selection signal ‘Yi_up’ to enable a columnselection line ‘CSL_up’ of the first memory bank Bank1. In the dataread/write operation on the second memory bank Bank2, the second columndecoder 12 generates, in response to the column address signals ‘Ya<2:7,9> and a strobe signal ‘strobe<1>, a column selection signal ‘Yi_dn’ toenable a column selection line ‘CSL_dn’ of the second memory bank Bank2.As shown in FIG. 1, the global input/output line GIO and an input/outputpad DQ are shared by the memory banks Bank 1 and Bank 2. In response totheir respective strobe signals ‘strobe<0:1>’, the first and secondinput/output drivers 21 and 22 amplify data stored in the first memorybank Bank1 and data stored in the second memory bank Bank2 respectively,and output the amplified data to outside of the semiconductor memoryapparatus via the global input/output line GIO and an input/output padDQ. During a data write operation, the first and second input/outputdrivers 21 and 22 amplify data received from outside via the pad DQ andthe global input/output line GIO and transfer the amplified data to thefirst memory bank Bank1 and to the second memory bank Bank2,respectively.

Thus, as is shown in FIG. 1 and described above, the same globalinput/output line GIO and the same pad DQ are assigned to each of thestacked memory banks Bank1 and Bank2 constituting the stacked bankstructure. However, separate column decoders 11 and 12 and separateinput/output drivers 21 and 22 are required for the stacked memory banksBank1 and Bank2. This is because the column selection line CSL_up of thefirst memory bank Bank1 and the column selection line CSL_dn of thesecond memory bank Bank2 are different from each other and the localinput/output line LIO_up of the first memory bank Bank1 and the localinput/output line LIO_dn of the second memory bank Bank2 are differentfrom each other.

The requirement of separate column decoders and input/output driversmakes it difficult to secure a lay-out margin of the semiconductormemory apparatus. A technique in which stacked memory banks share acolumn selection line has been proposed, but the technique causes anoverload on the column decoder facing the column selection line. Inaddition, no proper technique that allows the stacked memory banks toshare the input/output driver has been proposed until now.

SUMMARY OF THE INVENTION

Embodiments of the present invention include a semiconductor memoryapparatus and a data input/output method thereof, in which a pluralityof stacked memory banks can share a column decoder and an input/outputdriver.

In one embodiment of the present invention, a semiconductor memoryapparatus includes: a first bit line of a first memory bank; a firstmiddle input/output line configured to be electrically connected to thefirst bit line; a second bit line of a second memory bank; a secondmiddle input/output line configured to be electrically connected to thesecond bit line; and a shared local input/output line configured to beelectrically connected to the first and second middle input/outputlines, wherein a bank selection signal controls both the electricalconnection between the shared local input/output line and the firstmiddle input/output line and the electrical connection between theshared local input/output line and the second middle input/output line.

In another embodiment of the present invention, a semiconductor memoryapparatus includes: a shared column decoding unit configured tosimultaneously enable a column selection line of the first and secondmemory banks in response to a column address signal and a main strobesignal; an input/output switching unit configured to selectively andelectrically connect the first and second memory banks to a shared localinput/output line in response to a bank selection signal; and a sharedinput/output driving unit configured to amplify data transferred via theshared local input/output line to transfer the amplified data onto aglobal input/output line in a data read operation, and amplify datatransferred via the global input/output line to transfer the amplifieddata onto the shared local input/output line in a data write operation,in response to the main strobe signal.

In still another embodiment of the present invention, a semiconductormemory apparatus includes: a first memory bank; a second memory bank;first and second middle input/output lines configured to communicatewith the first and second memory banks in response to a column selectionsignal, respectively; and a shared local input/output line configured tobe electrically connected to the first and second middle input/outputlines, wherein the column selection signal of the first and secondmemory banks is configured to be simultaneously enabled, and theelectrical connection between the shared local input/output line and thefirst memory bank and the electrical connection between the shared localinput/output line and the second memory bank are selectively made inresponse to a bank selection signal.

In still another embodiment of the present invention, a datainput/output method of a semiconductor memory apparatus includes:enabling both of the column selection signals of the first and secondmemory banks when a data read/write operation is performed on the firstmemory bank and when the data read/write operation is performed on thesecond memory bank; and selectively and electrically connecting thefirst and second memory banks, on which the data read/write operation isto be actually performed, to a shared local input/output line.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with theattached drawings, in which;

FIG. 1 is a block diagram schematically showing a configuration of asemiconductor memory apparatus including stacked memory banks;

FIG. 2 is a block diagram schematically showing a configuration of asemiconductor memory apparatus including stacked memory banks accordingto an embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of an embodiment ofthe semiconductor memory apparatus of FIG. 2;

FIG. 4 is a diagram showing a configuration of an embodiment of thecontrol unit of FIG. 2;

FIG. 5 is a timing diagram showing an operation of a semiconductormemory apparatus shown in FIG. 1 in response to various commands; and

FIG. 6 is a timing diagram showing a data read/write operation of thesemiconductor memory apparatus of FIG. 2, according to an embodiment.

DETAILED DESCRIPTION

Hereinafter, a semiconductor memory apparatus and a data input/outputmethod thereof, according to the present invention, will be describedbelow with reference to the accompanying drawings through preferredembodiments.

FIG. 2 is a block diagram schematically showing a configuration of asemiconductor memory apparatus including a plurality of stacked memorybanks, according to an embodiment of the present invention. As shown inFIG. 2, the semiconductor memory apparatus 1 according to the embodimentincludes first and second memory banks Bank1 and Bank2, a shared columndecoding unit 100, a shared input/output driving unit 200, and a controlunit 300.

Hereinafter, it is assumed that the first and second memory banks Bank1and Bank2 of semiconductor memory apparatus 1 constitute the stackedbank structure. Since, in general, both a same global input/output lineand a same input/output pad are assigned to a plurality of memory banksconstituting the stacked bank structure, both a same global input/outputline GIO and a same input/output pad DQ are assigned to the first andsecond memory banks Bank1 and Bank2 in FIG. 2. Although only two memorybanks Bank1 and Bank2 are shown in FIG. 2, the embodiment is not limitedthereto, and the embodiment can also be applied to a case where three ormore memory banks are stacked.

The first and second memory banks Bank1 and Bank2 share a columnselection line CSL and local input/output lines LIO and LIOB. The columnselection line CSL is included for selection of a column of thesemiconductor memory apparatus 1. A column selection signal ‘Yi’generated from the column decoding unit 100 is provided via the columnselection line CSL. The local input/output lines LIO and LIOB are datainput/output lines which selectively transfer data stored in the firstmemory bank Bank1 and data stored in the second memory bank Bank2 ontothe global input/output line GIO, in a data read operation; andselectively transfer data transferred via the global input/output lineGIO to the first memory bank Bank1 and to the second memory bank Bank2,in a data write operation. The semiconductor memory apparatus 1 includesa number of the column selection lines CSL and a number of the localinput/output lines LIO and LIOB as much as the number of columns of thefirst and second memory banks Bank1 and Bank2.

Referring back to FIG. 1, the first and second memory banks Bank1 andBank2 constituting the stacked bank structure in FIG. 1 do not share acolumn selection line, and instead include separate column selectionlines CSL_up and CSL_dn. Therefore, in FIG. 1, the column decoders 11and 12 are responsive to their corresponding strobe signals ‘strobe<0:1>to decode the column address signals ‘Ya<2:7, 9>’, and then provide theseparate column selection signals ‘Yi_up’ and ‘Yi_dn’ to the memorybanks Bank1 and Bank2, thus indicating whether the data read/writeoperation is to be performed on the first memory bank Bank1 or on thesecond memory bank Bank2.

However, in FIG. 2, according to the embodiment of the presentinvention, the shared column decoding unit 100 simultaneously providesthe column selection signal ‘Yi’ via the column selection line CSL tothe memory banks Bank1 and Bank2, in response to column address signals‘Ya<2:7, 9>’ and a main strobe signal ‘mstrobe’. More specifically, inFIG. 2, since the first and second memory banks Bank1 and Bank2 sharethe column selection line CSL, the shared column decoding unit 100enables the column selection line CSL which the memory banks Bank1 andBank2 share, in response to the column address signals ‘Ya<2:7, 9>’ andthe main strobe signal ‘mstrobe’, when the semiconductor memoryapparatus 1 performs the data read/write operation on the first memorybank Bank1 and when the semiconductor memory apparatus 1 performs thedata read/write operation on the second memory bank Bank2. In otherwords, the shared column decoding unit 100 simultaneously provides thecolumn selection signal ‘Yi’ to the first and second memory banks Bank1and Bank2 in response to the column address signals ‘Ya<2:7, 9>’ whenthe main strobe signal ‘mstrobe’ is enabled. The main strobe signal‘mstrobe’ is generated by combining strobe signals (e.g., the strobesignals shown in FIG. 1), and will be described later.

The shared input/output driving unit 200 performs the data read/writeoperation in response to the main strobe signal ‘mstrobe’. Morespecifically, for a data read operation on the first memory bank Bank1and for a data read operation on the second memory bank Bank2, inresponse to the main strobe signal ‘mstrobe’, the shared input/outputdriving unit 200 receives and amplifies data on the shared localinput/output lines LIO and LIOB and transfers the amplified data ontothe global input/output line GIO. On the other hand, for the data writeoperation on the first memory bank Bank1 and for the data writeoperation on the second memory bank Bank2, in response to the mainstrobe signal ‘mstrobe’, the shared input/output driving unit 200amplifies the data on the global input/output line GIO and transfers theamplified data onto the shared local input/output lines LIO and LIOB.That is, in response to the main strobe signal ‘mstrobe’, the sharedinput/output driving unit 200 is enabled and performs the amplificationoperation, both when the semiconductor memory apparatus 1 performs thedata read/write operation on the first memory bank Bank1 and when thesemiconductor memory apparatus 1 performs the data read/write operationon the second memory bank Bank2. In an embodiment, the sharedinput/output driving unit 200 comprises a plurality of input/outputdrivers, as will be described in further detail later. Since the firstand second memory banks Bank1 and Bank2 share the local input/outputlines LIO and LIOB, the number of the input/output drivers can bereduced to half the number of the input/output drivers of theconventional art.

The shared local input/output lines LIO and LIOB are selectively andelectrically connected to the first memory bank Bank1 and the secondmemory bank Bank2 in response to the bank selection signals ‘Liorst_up’and ‘Liorst_dn’. More specifically, when the bank selection signals‘Liorst_up’ and ‘Liorst_dn’ are such that the first memory bank Bank1 isselected, the shared local input/output lines LIO and LIOB communicatewith only the first memory bank Bank1. On the other hand, when the bankselection signals ‘Liorst_up’ and ‘Liorst_dn’ are such that the secondmemory bank Bank2 is selected, the shared local input/output lines LIOand LIOB communicate with only the second memory bank Bank2. Therefore,the interval during which the shared local input/output lines LIO andLIOB are electrically connected to the first memory bank Bank1 does notoverlap with the interval during which the shared local input/outputlines LIO and LIOB are electrically connected to the second memory bankBank2.

As such, even though the first and second memory banks Bank1 and Bank2share the column decoding unit and the input/output driving unit, thesemiconductor memory apparatus 1 according to the embodiment canproperly perform data read/write operations without a data collision.This is because the shared local input/output lines LIO and LIOBselectively communicate with the first and second memory banks Bank1 andBank2 in response to the bank selection signals ‘Liorst_up’ and‘Liorst_dn’.

As shown in FIG. 2, the semiconductor memory apparatus 1 according to anembodiment can further include the control unit 300 configured togenerate the main strobe signal ‘mstrobe’ and the bank selection signals‘Liorst_up’ and ‘Liorst_dn’ in response to the read/write command‘RD/WT’ and a bank address signal ‘BA’. The read/write command ‘RD/WT’is a signal that instructs the semiconductor memory apparatus 1 toperform the data read/write operation and can be inputted from theoutside of the semiconductor memory apparatus 1 via pads. The bankaddress signal ‘BA’ is a signal that includes information for selectinga memory bank on which the data read/write operation is to be actuallyperformed and can be inputted from the outside via pads. Therefore, thecontrol unit 300 performs the function of combining and differentiatingbetween information on the data read/write operations of the respectivefirst and second memory banks Bank1 and Bank2. In particular, both whenthe semiconductor memory apparatus 1 performs the data read/writeoperation on the first memory bank Bank1 and when the semiconductormemory apparatus 1 performs the data read/write operation on the secondmemory bank Bank2, the control unit 300 generates a main strobe signal‘mstrobe’ instructing the shared column decoding unit to provide thecolumn selection signal ‘Yi’, and the column selection signal ‘Yi’ isprovided to both of the memory banks Bank1 and Bank2. The main strobesignal ‘mstrobe’ generated by the control unit 300 also enables theshared input/output driving unit 200 to perform the amplificationoperation. As explained above, even though the column selection signal‘Yi’ is provided to both the first and second memory banks Bank1 andBank2 simultaneously, the bank selection signals ‘Liorst_up’ and‘Liorst_dn’ generated from the control unit 300 can specify the intendedmemory bank that the data read/write operation is to be actuallyperformed on.

FIG. 3 is a circuit diagram showing a configuration of the semiconductormemory apparatus 1 of FIG. 2, according to an embodiment of the presentinvention. As shown in FIG. 3, the semiconductor memory apparatus 1includes first bit lines BL_up and BLB_up, second bit lines BL_dn andBLB_dn, first to fourth middle input/output lines MIO1 to MIO4 and MIO1Bto MIO4B, shared local input/output lines LIO and LIOB, a sharedinput/output driver 210, and first to fourth precharge units 411 to 414.In FIG. 3, in order to avoid obscuring the drawing, the shared columndecoding unit 100 of FIG. 2 is not shown, but the column selectionsignal ‘Yi’ generated from the shared column decoding unit 100 is showninstead.

In FIG. 3, the first bit lines BL_up and BLB_up are electricallyconnected to the first memory bank Bank1 to receive/transfer datafrom/to the first memory bank Bank1. In an embodiment, the first bitlines BL_up and BLB_up intersect with a plurality of word lines forminga plurality of memory cells. Although actual wiring connections betweenthe first bit lines BL_up and BLB_up and the word lines are not shown inFIG. 3 to avoid obscuring the invention, the first bit lines BL_up andBLB_up may intersect with a total of 8 word lines. However, it should beunderstood that the embodiment is not limited thereto. Likewise, thesecond bit lines BL_dn and BLB_dn are electrically connected to thesecond memory bank Bank2 to receive/transfer data from/to the secondmemory bank Bank2. In an embodiment, the second bit lines BL_dn andBLB_dn are also coupled to 8 word lines.

As shown in FIG. 3, first to fourth column switches CSW1 to CSW4 areinterposed between the first and second bit lines BL_up, BLB_up, BL_dnand BLB_dn and the first to fourth middle input/output lines MIO1 toMIO4 and MIO1B to MIO4B. When the column selection signal ‘Yi’ isenabled, the first to fourth column switches CSW1 to CSW4 are all turnedon, and thus an electrical connection is established between the firstand second bit lines BL_up, BLB_up, BL_dn and BLB_dn and the first tofourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B. Inaddition, first to fourth input/output switching units IOSW1 to IOSW4are interposed between the first to fourth middle input/output linesMIO1 to MIO4, MIO1B to MIO4B and the shared local input/output lines LIOand LIOB. In an embodiment, the respective first to fourth input/outputswitching units IOSW1 to IOSW4 comprise NMOS transistors similar to thefirst to fourth column switches CSW1 to CSW4. Herein, the bank selectionsignals ‘Liorst_up’ and ‘Liorst_dn’ control whether the respective firstto fourth input/output switching units IOSW1 to IOSW4 are turned on oroff. In detail, if the bank selection signals ‘Liorst_up’ and‘Liorst_dn’ are generated by the control unit to select the first memorybank Bank1 (i.e., for example, when the up bank selection signal‘Liorst_up’ is enabled) the first and second input/output switchingunits IOSW1 and IOSW2 are both turned on establishing an electricalconnection between the first and second middle input/output lines MIO1,MIO1B, MIO2, MIO2B and the shared local input/output lines LIO and LIOB.Conversely, when the bank selection signals ‘Liorst_up’ and ‘Liorst_dn’are generated by the control unit to select the second memory bank Bank2(i.e., for example, if the down bank selection signal ‘Liorst_dn’ isenabled) the third and fourth input/output switching units IOSW3 andIOSW4 are both turned on establishing an electrical connection betweenthe third and fourth middle input/output lines MIO3, MIO3B, MIO4, MIO4Band the shared local input/output lines LIO and LIOB.

The shared local input/output lines LIO and LIOB are coupled to theshared input/output driver 210, and an output of the shared input/outputdriver 210 is coupled to the global input/output line GIO.

Accordingly, both when the semiconductor memory apparatus 1 performs adata read/write operation on the first memory bank Bank1 and when thesemiconductor memory apparatus 1 performs a data read/write operation onthe second memory bank Bank2, the first and second bit lines BL_up,BLB_up, BL_dn and BLB_dn are electrically connected to the first tofourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B,respectively, because the column selection signal ‘Yi’ is enabledirrespective of which memory bank Bank1 or Bank2 the read/writeoperation is associated with.

When the semiconductor memory apparatus 1 performs the data read/writeoperation on the first memory bank Bank1, the up bank selection signal‘Liorst_up’ is enabled, and subsequently the first and secondinput/output switching units IOSW1 and IOSW2 are both turned on, and onthe other hand, the third and fourth input/output switching units IOSW3and IOSW4 are both turned off. Therefore, the first and second middleinput/output lines MIO1, MIO1B, MIO2 and MIO2B are electricallyconnected to the shared local input/output lines LIO and LIOB, and onthe other hand, the third and fourth middle input/output lines MIO3,MIO3B, MIO4 and MIO4B are electrically disconnected from the sharedlocal input/output lines LIO and LIOB. Therefore, even though each ofthe first to fourth column switches CSW1 to CSW4 of the memory banksBank1 and Bank2 are turned on in response to the column selection signal‘Yi’ generated by the column decoding unit 100, whereby the first andsecond bit lines BL_up, BLB_up, BL_dn and BLB_dn are electricallyconnected to the first to fourth middle input/output lines MIO1 to MIO4and MIO1B to MIO4B, the shared local input/output lines LIO and LIOB areelectrically connected to only the first and second middle input/outputlines MIO1, MIO1B, MIO2 and MIO2B via the first and second input/outputswitching units IOSW1 and IOSW 2 among the first to fourth middleinput/output lines MIO1 to MIO4 and MIO1B to MIO4B. Accordingly, thesemiconductor memory apparatus 1 can perform the data read/writeoperation on the first memory bank Bank1 successfully.

Conversely, when the semiconductor memory apparatus 1 performs the dataread/write operation on the second memory bank Bank2, the down bankselection signal ‘Liorst_dn’ is enabled, and subsequently the first andsecond input/output switching units IOSW1 and IOSW2 are both turned off,and on the other hand, the third and fourth input/output switching unitsIOSW3 and IOSW4 are both turned on. Therefore, the first and secondmiddle input/output lines MIO1, MIO1B, MIO2 and MIO2B are electricallydisconnected from the shared local input/output lines LIO and LIOB, andon the other hand, the third and fourth middle input/output lines MIO3,MIO3B, MIO4 and MIO4B are electrically connected to the shared localinput/output lines LIO and LIOB. Therefore, even though each of thefirst to fourth column switches CSW1 to CSW4 of the memory banks Bank1and Bank2 are turned on in response to the column selection signal ‘Yi’generated by the column decoding unit 100, whereby the first and secondbit lines BL_up, BLB_up, BL_dn and BLB_dn are electrically connected tothe first to fourth middle input/output lines MIO1 to MIO4 and MIO1B toMIO4B, the shared local input/output lines LIO and LIOB are electricallyconnected to only the third and fourth middle input/output lines MIO3,MIO3B, MIO4 and MIO4B among the first to fourth middle input/outputlines MIO1 to MIO4 and MIO1B to MIO4B via the third and fourthinput/output switching units IOSW3 and IOSW4. Accordingly, thesemiconductor memory apparatus 1 can perform the data read/writeoperation on the second memory bank Bank2 successfully.

Herein, it is preferable that the respective pulse widths of the bankselection signals ‘Liorst_up’ and ‘Liorst_dn’ are wider than the pulsewidth of the column selection signal ‘Yi’. More specifically, it ispreferable that the respective bank selection signals ‘Liorst_up’ and‘Liorst_dn’ are enabled earlier than the column selection signal ‘Yi’and are disabled later than the column selection signal ‘Yi’. When adata read/write operation performed on the first memory bank Bank1 ofthe semiconductor memory apparatus 1, early enablement of the up bankselection signal ‘Liorst_up’ with respect to the column selection signal‘Yi’ allows the semiconductor memory apparatus 1 to turn on the firstand second input/output switching units IOSW1 and IOSW2 earlier than thecorresponding column switches CSW1 and CSW2 and be ready to perform thedata read/write operation. Further, late disablement of the up bankselection signal ‘Liorst_up’ with respect to the column selection signal‘Yi’ allows the semiconductor memory apparatus 1 to substantiallymaintain the turn-on state of the first and second input/outputswitching units IOSW1 and IOSW2 until the data read/write operation isfinished, thereby allowing the data read/write operation to be completedsafely. Likewise, when a data read/write operation is performed on thesecond memory bank Bank2 of the semiconductor memory apparatus 1, earlyenablement of the down bank selection signal ‘Liorst_dn’ with respect tothe column selection signal ‘Yi’ allows the semiconductor memoryapparatus 1 to turn on the third and fourth input/output switching unitsIOSW3 and IOSW4 earlier than the corresponding column switches CSW3 andCSW4 and be ready to perform the data read/write operation. Further,late disablement of the down bank selection signal ‘Liorst_dn’ withrespect to the column selection signal ‘Yi’ allows the semiconductormemory apparatus 1 to substantially maintain the turn-on state of thethird and fourth input/output switching units IOSW3 and IOSW4 until thedata read/write operation is finished, thereby allowing the dataread/write operation to be completed safely.

Referring to FIG. 3, the first to fourth precharge units 411 to 414precharge the first to fourth middle input/output lines MIO1 to MIO4 andMIO1B to MIO4B, respectively. That is, when the word line is disabled,the first to fourth precharge units 411 to 414 precharge the first tofourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B inresponse to precharge signals ‘BLEQ_up<0:7>’ and ‘BLEQ_dn<0:7>’,respectively. Since the first to fourth precharge units 411 to 414 canbe readily implemented, a detailed description thereof will be omitted.

FIG. 3 shows an exemplary wiring connection of input/output lines of asingle column among a plurality of columns of the first and secondmemory banks Bank1 and Bank2. Therefore, with respect to the first andsecond memory banks Bank1 and Bank2, the configuration shown in FIG. 3is repeated in plurality as much as the number of the columns of thememory banks Bank1 and Bank2 in an embodiment of the present invention.Further, the shared input/output driver 210 is included in plurality asmuch as the number of the columns of the memory banks Bank1 and Bank2 inan embodiment of the present invention. Accordingly the plurality of theshared input/output drivers 210 would constitute the shared input/outputdriving unit 200 shown in FIG. 2.

FIG. 4 is a diagram showing a configuration of an embodiment of thecontrol unit 300 shown in FIG. 2. As shown in FIG. 4, the control unit300 includes a decoder 310, first and second delay units 321 and 322,first and second strobe signal generating units 331 and 332, a strobecombination unit 340, and a bank selection signal generating unit 350.

Referring to FIG. 4, the decoder 310 decodes the read/write command‘RD/WT’ and the bank address signal ‘BA’ to generate first and secondinternal strobe signals ‘WT_up’, ‘RD_up’ and ‘WT_dn’, ‘RD_dn’. Since theread/write command ‘RD/WT’ is a signal that instructs the semiconductormemory apparatus 1 to perform a data read/write operation and the bankaddress signal ‘BA’ includes information on which memory bank the dataread/write operation is to be actually performed, the first internalstrobe signals ‘WT_up’ and ‘RD_up’ include information on the dataread/write operation of the first memory bank Bank1, and the secondinternal strobe signals ‘WT_dn’ and ‘RD_dn’ include information on thedata read/write operation of the second memory bank Bank2. Since thedecoder 310 can be implemented by those skilled in the art, a detaileddescription thereon will be omitted. Hereinafter, for convenience ofdescription, the first internal strobe signals ‘WT_up’ and ‘RD_up’associated with a data read/write operation on the first memory bankBank1 will be represented as a signal ‘T1’, and the second internalstrobe signals ‘WT_dn’ and ‘RD_dn’ associated with a data read/writeoperation on the second memory bank Bank2 will be represented as asignal ‘T1′’.

As shown in FIG. 4, the first delay unit 321 according to an embodimentincludes seven inverters coupled in series and delays the first internalstrobe signal ‘T1’ sequentially. Similarly, the second delay unit 322according to an embodiment includes seven inverters coupled in seriesand delays the second internal strobe signal ‘T1′’ sequentially. Itshould be understood that the present invention is not limited to seveninverters for the first and second delay units 321, and the number ofinverters may be adjusted according to the desired pulse width of the upand down band selection signals ‘Liorst_up’ and ‘Liorst_down’ as will beapparent from the description below.

The first strobe signal generating unit 331 receives delay signals ‘T2b’ and ‘T3 b’ and generates the first strobe signal ‘strobe<0>’. In anembodiment, the first strobe signal generating unit 331 includes a firstNAND gate ND1 receiving the delay signals ‘T2 b’ and ‘T3 b’, and firstand second inverters IV1 and IV2 sequentially inverting the output ofthe first NAND gate ND1. Similarly, the second strobe signal generatingunit 332 receives delay signals ‘T2′b’ and ‘T3′b’ and generates thesecond strobe signal ‘strobe<1>’. In an embodiment, the second strobesignal generating unit 332 includes a second NAND gate ND2 receiving thedelay signals ‘T2′b’ and ‘T3′b’, and third and fourth inverters IV3 andIV4 sequentially inverting an output of the second NAND gate ND2.

The strobe combination unit 340 combines the first and second strobesignals ‘strobe<0:1>’ to generate the main strobe signal ‘mstrobe’. Thestrobe combination unit 340 can, in an embodiment, be implemented withan OR gate receiving the first and second strobe signals ‘strobe<0:1>’to generate the main strobe signal ‘mstrobe’.

In an embodiment, the bank selection signal generating unit 350 includesthird and fourth NAND gates ND3 and ND4 and fifth to eighth invertersIV5, IV6, IV7 and IV8. The third NAND gate ND3 receives delay signals‘T1 b’ and ‘T4 b’; and therefore, the up bank selection signal‘Liorst_up’ generated by the bank selection signal generating unit 350has a pulse width wider than that of the first strobe signal‘strobe<0>’. Likewise, since the fourth NAND gate ND4 receives delaysignals ‘T1′b’ and ‘T4′b’, the down bank selection signal ‘Liorst_dn’generated from the bank selection signal generating unit 350 has a pulsewidth wider than that of the second strobe signal ‘strobe<1>’.

It will be apparent to those skilled in the art that the control unit300 can be implemented in a variety of logic configurations. Inaddition, it will be understood that the strobe combination unit 340 andthe bank selection signal generating unit 350 included in the controlunit 300 may alternatively be included in the shared column decodingunit 100 or the shared input/output driving unit 200 or otheralternative implementations.

FIG. 5 is a timing diagram showing an operation of a conventionalsemiconductor memory apparatus in response to various commands. As shownin FIG. 5, the conventional semiconductor memory apparatus receives thevarious commands and performs various operations in response to thecommands. In response to the commands inputted to the conventionalsemiconductor memory apparatus, the conventional semiconductor memoryapparatus receives a row address strobe signal ‘/RAS’, a column addressstrobe signal ‘/CAS’, a write enable signal ‘/WE’, and a chip selectionsignal ‘/CS’. In general, a command buffer receives the signals ‘/RAS’,‘/CAS’, ‘/WE’ and ‘/CS’ corresponding to the commands and a clock enablesignal ‘CKE’ (not shown) to generate internal command signals. Withreference to FIG. 5, if an active command ‘ACT’ is applied to theconventional semiconductor memory apparatus, the conventionalsemiconductor memory apparatus receives the enabled row address strobesignal ‘/RAS’ and the enabled write enable signal ‘/WE’ and therebyreceives a row address signal ‘Row ADD’. Therefore, a word line selectedin response to the row address signal ‘Row ADD’ is enabled, and theconventional semiconductor memory apparatus enters an active mode.Afterwards, when the read/write command ‘RD/WT’ is applied, the columnaddress strobe signal ‘/CAS’ is enabled, and the conventionalsemiconductor memory apparatus receives a column address signal ‘ColumnADD’. Therefore, a column selection line selected in response to thecolumn address signal ‘Column ADD’ is enabled, and consequently theconventional semiconductor memory apparatus can perform the dataread/write operation. At this time, the strobe signals ‘strobe<0:1>’ aregenerated in response to the read/write command ‘RD/WT’. Afterwards,when a precharge command ‘PCG’ is applied, the enabled word line isdisabled and the conventional semiconductor memory apparatus enters astand-by mode. The above-mentioned operation is performed repetitively,and thus the data input/output operation can be performed.

With reference to FIGS. 3 to 5, the reason that the semiconductor memoryapparatus 1 according to an embodiment generates the bank selectionsignals ‘Liorst_up’ and ‘Liorst_dn’ by using the read/write command‘RD/WT’ will now be explained.

In the conventional art, the plurality of stacked memory banks cannotshare the local input/output lines, because the conventionalsemiconductor memory apparatus controls switching units using a signalgenerated from the active command ‘ACT’, which allows the row addresssignal ‘Row ADD’ to be inputted to the conventional semiconductor memoryapparatus. Herein, if the semiconductor memory apparatus 1 shown inFIGS. 2-4 were to control the first to fourth input/output switchingunits IOSW1 to IOSW4 using a signal generated from the active command‘ACT’ as is done in the conventional art, the first to fourthinput/output switching units IOSW1 to IOSW4 would be turned-on duringthe entire time interval of the active mode of the semiconductor memoryapparatus 1. Because the semiconductor memory apparatus 1 simultaneouslyenables the column selection line CSL of the memory banks Bank1 andBank2 during a data read operation by using the shared column decodingunit 100, the data stored in the different memory banks, i.e., Bank1 andBank2, would be simultaneously transferred onto the shared localinput/output lines LIO and LIOB via the first to fourth input/outputswitching units IOSW1 to IOSW4. This causes a collision between the datatransferred from the first memory bank Bank1 onto the shared localinput/output line and the data transferred from the second memory bankBank2 onto the shared local input/output line. As such, according to thepractices of the conventional art, the plurality of the stacked memorybanks cannot share the column decoder, the column selection line, thelocal input/output line and the input/output driver.

However, since the semiconductor memory apparatus 1 according toembodiments of the present invention controls the first to fourthinput/output switching units IOSW1 to IOSW4 in response to the bankselection signals ‘Liorst_up’ and ‘Liorst_dn’, which are generated fromthe read/write command ‘RD/WT’, the above-mentioned data collision doesnot occur. That is, even though the plurality of the stacked memorybanks Bank1 and Bank2 share the local input/output lines LIO and LIOB,data collision does not occur because the semiconductor memory apparatus1 selectively turns on the respective first to fourth input/outputswitching units IOSW1 to IOSW4 so that the corresponding middleinput/output lines are connected during the interval in which the dataread/write operation is actually performed rather than during the entireinterval of the active mode. Accordingly, in FIG. 3, even thoughspecific word lines of the memory banks Bank1 and Bank2 aresimultaneously enabled and the column selection signals ‘Yi’ of thememory banks Bank1 and Bank2 are simultaneously enabled during dataread/write operations for both the first memory bank Bank1 and thesecond memory bank Bank2, collision between the data transferred fromthe different memory banks Bank1 and Bank2 can be avoided. The first andsecond input/output switching units IOSW1 and IOSW2 are both turned ononly during the interval during which the data read/write operation isactually performed on the first memory bank Bank1, in response to the upbank selection signal ‘Liorst_up’; and conversely, the third and fourthinput/output switching units IOSW3 and IOSW4 are both turned on onlyduring the interval during which the data read/write operation isactually performed on the second memory bank Bank2, in response to thedown bank selection signal ‘Liorst_dn’.

A data read/write operation of the semiconductor memory apparatus 1according to an embodiment of the present invention will now bedescribed with reference to FIGS. 2 to 4 and 6.

Referring to FIG. 4, the decoder 310 decodes the read/write command‘RD/WT’ and the bank address signal ‘BA’ to generate the first andsecond internal strobe signals ‘WT_up’, ‘RD_up’ and ‘WT_dn’, ‘RD_dn’.The first strobe signal generating unit 331 generates the first strobesignal ‘strobe<0>’ in response to the first internal strobe signals‘WT_up’ and ‘RD_up’, and the second strobe signal generating unit 332generates the second strobe signal ‘strobe<1>’ in response to the secondinternal strobe signals ‘WT_dn’ and ‘RD_dn’. The strobe combination unit340 combines the first and second strobe signals ‘strobe<0:1>’ togenerate the main strobe signal ‘mstrobe’. In addition, the bankselection signal generating unit 350 generates the up bank selectionsignal ‘Liorst_up’ having the pulse width wider than the pulse width ofthe first strobe signal ‘strobe<0>’, and generates the down bankselection signal ‘Liorst_dn’ having the pulse width wider than the pulsewidth of the second strobe signal ‘strobe<1>’.

FIG. 6 is a timing diagram showing the data read/write operation of thesemiconductor memory apparatus 1 of FIG. 2, according to an embodimentof the present invention. In FIG. 6, the first write command ‘WT’ andthe first read command ‘RD’ (from left) are both associated with thefirst memory bank Bank1 and the second write command ‘WT’ and the secondread command ‘RD’ (from left) are both associated with the second memorybank Bank2.

Firstly, if the first write command ‘WT’ is applied to the semiconductormemory apparatus 1, the shared column decoding unit 100 enables thecolumn selection signals ‘Yi’ of both the memory banks Bank1 and Bank2in response to the first pulse signal of the main strobe signal‘mstrobe’. Therefore, in FIG. 3, since the first to fourth columnswitches CSW1 to CSW4 are all turned on, the first and second bit linesBL_up, BLB_up, BL_dn and BLB_dn are electrically connected to the firstto fourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B. Atthis time, only the first and second input/output switching units IOSW1and IOSW2 among the input/output switching units IOSW1 to IOSW4 areturned on in response to the enabled up bank selection signal‘Liorst_up’; and therefore, only the first and second middleinput/output lines MIO1, MIO1B, MIO2 and MIO2B among the middleinput/output lines MIO1 to MIO4 and MIO1B to MIO4B are electricallyconnected to the shared local input/output lines LIO and LIOB.Therefore, even though the first to fourth column switches CSW1 to CSW4of the memory banks Bank1 and Bank2 are all turned on in response to thecolumn selection signal ‘Yi’, only the first memory bank Bank1 iselectrically connected to the shared local input/output lines LIO andLIOB. Since the shared input/output driving unit 200 is enabled inresponse to the main strobe signal ‘mstrobe’, the shared input/outputdriving unit 200 amplifies data transferred via the pad DQ and theglobal input/output line GIO, and transfers the amplified data onto theshared local input/output lines LIO and LIOB. Then, since the sharedlocal input/output lines LIO and LIOB are electrically connected to thefirst bit lines BL_up and BLB_up, the transferred data on the sharedlocal input/output lines LIO and LIOB can be transferred onto the firstbit lines BL_up and BLB_up, and consequently can be stored in a memorycell of the first memory bank Bank1 coupled to the first bit lines BL_upand BLB_up.

Secondly, on the other hand, if the second write command ‘WT’ is appliedto the semiconductor memory apparatus 1, the shared column decoding unit100 enables the column selection signals ‘Yi’ of both the memory banksBank1 and Bank2 in response to the second pulse signal of the mainstrobe signal ‘mstrobe’. Therefore, in FIG. 3, since the first to fourthcolumn switches CSW1 to CSW4 are all turned on, the first and second bitlines BL_up, BLB_up, BL_dn and BLB_dn are electrically connected to thefirst to fourth middle input/output lines MIO1 to MIO4 and MIO1B toMIO4B. At this time, only the third and fourth input/output switchingunits IOSW3 and IOSW4 among the input/output switching units IOSW1 toIOSW4 are turned on in response to the enabled down bank selectionsignal ‘Liorst_dn’; and therefore, only the third and fourth middleinput/output lines MIO3, MIO3B, MIO4 and MIO4B among the middleinput/output lines MIO1 to MIO4 and MIO1B to MIO4B are electricallyconnected to the shared local input/output lines LIO and LIOB.Therefore, even though the first to fourth column switches CSW1 to CSW4of the memory banks Bank1 and Bank2 are all turned on in response to thecolumn selection signal ‘Yi’, only the second memory bank Bank2 iselectrically connected to the shared local input/output lines LIO andLIOB. Since the shared input/output driving unit 200 is enabled inresponse to the main strobe signal ‘mstrobe’, the shared input/outputdriving unit 200 amplifies data transferred via the pad DQ and theglobal input/output line GIO, and transfers the amplified data onto theshared local input/output lines LIO and LIOB. Then, since the sharedlocal input/output lines LIO and LIOB are electrically connected to thesecond bit lines BL_dn and BLB_dn, the transferred data on the sharedlocal input/output lines LIO and LIOB can be transferred onto the secondbit lines BL_dn and BLB_dn, and consequently can be stored in a memorycell of the second memory bank Bank2 coupled to the second bit linesBL_dn and BLB_dn.

Thirdly, if the first read command ‘RD’ is applied to the semiconductormemory apparatus 1, the first bit lines BL_up and BLB_up areelectrically connected to the shared local input/output lines LIO andLIOB as described above. Therefore, the shared input/output driving unit200 amplifies data transferred from the memory cell of the first memorybank Bank1 via the first bit lines BL_up and BLB_up and the shared localinput/output lines LIO and LIOB, and outputs the amplified data tooutside of the semiconductor memory apparatus 1 via the globalinput/output line GIO and a pad DQ.

Finally, on the other hand, if the second read command ‘RD’ is appliedto the semiconductor memory apparatus 1, the second bit lines BL_dn andBLB_dn are electrically connected to the shared local input/output linesLIO and LIOB as described above. Therefore, the shared input/outputdriving unit 200 amplifies data transferred from the memory cell of thesecond memory bank Bank2 via the second bit lines BL_dn and BLB_dn andthe shared local input/output lines LIO and LIOB, and outputs theamplified data to outside of the semiconductor memory apparatus 1 viathe global input/output line GIO and a pad DQ.

As such, in the semiconductor memory apparatus and the data input/outputmethod thereof according to an embodiment of the present invention, aplurality of stacked memory banks can share a column decoder and aninput/output driver without data collision, thereby improving thelay-out margin of the semiconductor memory apparatus.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the device and method describedherein should not be limited based on the described embodiments. Rather,the apparatus described herein should only be limited in light of theclaims that follow when taken in conjunction with the above descriptionand accompanying drawings.

1. A semiconductor memory apparatus comprising: a first bit line of afirst memory bank; a first middle input/output line electricallyconnected to the first bit line; a second bit line of a second memorybank; a second middle input/output line electrically connected to thesecond bit line; and a shared local input/output line selectivelyelectrically connected to each of the first and second middleinput/output lines, wherein a bank selection signals control theelectrical connection between the shared local input/output line and thefirst middle input/output line and the electrical connection between theshared local input/output line and the second middle input/output line.2. The semiconductor memory apparatus of claim 1, wherein the firstmiddle input/output line is electrically connected to the first bit lineand the second middle input/output line is electrically connected to thesecond bit line in response to a column selection signal, such that thefirst middle input/output line is electrically connected to the firstbit line and the second middle input/output line is electricallyconnected to the second bit line simultaneously.
 3. The semiconductormemory apparatus of claim 2, wherein the interval during which the firstmiddle input/output line is electrically connected to the shared localinput/output line does not overlapped with the interval during which thesecond middle input/output line is electrically connected to the sharedlocal input/output line.
 4. The semiconductor memory apparatus of claim1, wherein the bank selection signal includes information indicatingwhich one of the first and second memory banks is associated with a dataread/write operation.
 5. The semiconductor memory apparatus of claim 1,further comprising a control unit generating the one or more bankselection signals in response to a read/write command and a bank addresssignal.
 6. The semiconductor memory apparatus of claim 2, wherein thebank selection signal is configured to be enabled earlier than thecolumn selection signal, and to be disabled later than the columnselection signal.
 7. A semiconductor memory apparatus comprising: ashared column decoding unit configured to simultaneously enable a columnselection line of the first and second memory banks in response to acolumn address signal and a main strobe signal; an input/outputswitching unit configured to selectively electrically connect the firstand second memory banks to a shared local input/output line in responseto a bank selection signal; and a shared input/output driving unitconfigured to amplify data transferred via the shared local input/outputline and transfer the amplified data onto a global input/output line ina data read operation, and to amplify data transferred via the globalinput/output line and transfer the amplified data onto the shared localinput/output line in a data write operation, in response to the mainstrobe signal.
 8. The semiconductor memory apparatus of claim 7, whereinthe bank selection signal includes information indicating which one ofthe first and second memory banks is associated with the data read/writeoperation.
 9. The semiconductor memory apparatus of claim 7, wherein themain strobe signal includes information on the data read or data writeoperation of the first and second memory banks.
 10. The semiconductormemory apparatus of claim 7, wherein the semiconductor memory apparatusfurther includes a control unit configured to generate the bankselection signal and the main strobe signal in response to a read/writecommand and a bank address signal.
 11. The semiconductor memoryapparatus of claim 7, wherein the bank selection signal is configured tobe enabled earlier than a column selection signal, and to be disabledlater than the column selection signal.
 12. A semiconductor memoryapparatus comprising: a first memory bank; a second memory bank; firstand second middle input/output lines configured to communicate with thefirst and second memory banks respectively, in response to a columnselection signal; and a shared local input/output line selectivelyelectrically connected to the first and second middle input/outputlines, wherein the column selection signal simultaneously enablescommunication of the first and second middle input/output lines with thefirst and second memory banks , and the electrical connection betweenthe shared local input/output line and the first memory bank and theelectrical connection between the shared local input/output line and thesecond memory bank are made selectively in response to a bank selectionsignal.
 13. The semiconductor memory apparatus of claim 12, furthercomprising a column selection switching unit configured to transfer datastored in the first memory bank onto the first middle input/output linein a data read operation and transfer data transferred via the firstmiddle input/output line to the first memory bank in a data writeoperation, when the column selection signal is enabled.
 14. Thesemiconductor memory apparatus of claim 12, further comprising a columnselection switching unit configured to transfer data stored in thesecond memory bank onto the second middle input/output line in a dataread operation and transfer data transferred via the second middleinput/output line to the second memory bank in a data write operation,when the column selection signal is enabled.
 15. The semiconductormemory apparatus of claim 12, wherein the bank selection signal includesinformation indicating which one of the first and second memory banks isassociated with a data read/write operation.
 16. The semiconductormemory apparatus of claim 12, further comprising a shared input/outputdriving unit configured to amplify data transferred via the shared localinput/output line and transfer the amplified data onto a globalinput/output line in a data read operation, and to amplify datatransferred via the global input/output line and transfer the amplifieddata onto the shared local input/output line in a data write operation,in response to a main strobe signal.
 17. The semiconductor memoryapparatus of claim 16, further comprising a control unit configured togenerate the bank selection signal and the main strobe signal inresponse to a read/write command and a bank address signal.
 18. A datainput/output method of a semiconductor memory apparatus comprising firstand second memory banks and a local input/output line shared by thefirst and second memory banks, the data input/output method comprising:enabling a column selection signal of the first memory bank and thesecond memory bank when a data read/write operation is performed on thefirst memory bank and also when a data read/write operation is performedon the second memory bank; and electrically connecting only one of thefirst and second memory banks to the shared local input/output linedepending upon on which of the first and second memory banks a dataread/write operation is to be performed.
 19. The data input/outputmethod of claim 18, wherein the column selection signal of the firstmemory bank and the second memory bank is enabled in response to a mainstrobe signal and a column address signal.
 20. The data input/outputmethod of claim 19, wherein the main strobe signal includes informationon the data read/write operation of the first and second memory banks.21. The data input/output method of claim 18, wherein electricallyconnecting only one of the first and second memory banks to the sharedlocal input/output line is performed in response to a bank selectionsignal including information on which one of the first and second memorybanks is associated with the data read/write operation.
 22. The datainput/output method of claim 19, wherein the data input/output methodfurther comprises enabling a shared input/output driving unit coupled tothe shared local input/output line in response to the main strobe signalwhen the data read/write operation is performed on the first memory bankand when the data read/write operation is performed on the second memorybank.
 23. The data input/output method of claim 22, further comprising:amplifying, by the shared input/output driving unit, data transferredvia the shared local input/output line and transferring, by the sharedinput/output driving unit, the amplified data onto a global input/outputline in the data read operation, in response to the main strobe signal;and amplifying, by the shared input/output driving unit, datatransferred via the global input/output line and transferring, by theshared input/output driving unit the amplified data onto the sharedlocal input/output line in the data write operation, in response to themain strobe signal.